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ltc2360/ltc2361/ltc2362 1 236012fa typical application features applications description 100ksps/250ksps/500ksps, 12-bit serial adcs in tsot-23 the ltc ? 2360/ltc2361/ltc2362 are 100ksps/250ksps/ 500ksps, 12-bit, sampling a/d converters that draw only 0.5ma, 0.75ma and 1.1ma, respectively, from a single 3v supply. the supply current drops at lower sampling rates because these devices automatically power down after conversions. the full-scale input of the ltc2360/ ltc2361/ltc2362 is 0v to v dd or v ref . these adcs are available in tiny 6- and 8-lead tsot-23 packages. the serial interface, tiny tsot-23 package and extremely high sample rate-to-power ratio make the ltc2360/ ltc2361/ltc2362 ideal for compact, low power, high speed systems. the high impedance single-ended analog input and the ability to operate with reduced spans (down to 1.4v full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. single 3v supply, 500ksps, 12-bit sampling adc n 12-bit resolution n low noise: 73db snr n low power dissipation: 1.5mw at 100ksps n 100ksps/250ksps/500ksps sampling rates n single supply 2.35v to 3.6v operation n no data latency n sleep mode with 0.1a typical supply current n dedicated external reference (tsot23-8) n 1v to 3.6v digital output supply (tsot23-8) n spi/microwire? compatible serial i/o n guaranteed operation from C40c to 125c n tiny 6- and 8-lead tsot-23 packages n communication systems n data acquisition systems n handheld portable devices n uninterrupted power supplies n battery-operated systems n automotive supply current vs sample rate v dd v ref gnd a in conv sck sdo ov dd ltc2362 2.2f 3v 236012 ta01a serial data link to asic, pld, mpu, dsp or shift registors digital output supply 1v to v dd analog input 0v to 3v 2.2f sample rate (ksps) supply current (a) 236012 ta01b 1200 1000 800 400 600 200 0 1 100 1000 10 v dd = 3.6v t a = 25 c ltc2361 ltc2362 ltc2360 12-bit tsot23-6/-8 adc family data output rate 3msps 1msps 500ksps 250ksps 100ksps part number ltc2366 ltc2365 ltc2362 ltc2361 ltc2360 l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2360/ltc2361/ltc2362 2 236012fa absolute maximum ratings supply voltage (v dd ) ..................................................4v supply voltage (ov dd ) ................ min (v dd + 0.3v, 4.0v) v ref and analog input voltage (note 3) .........................................C0.3v to (v dd + 0.3v) digital input voltage ......................C0.3v to (v dd + 0.3v) digital output voltage ...................C0.3v to (v dd + 0.3v) power dissipation ...............................................100mw (notes 1, 2) order information v dd 1 v ref 2 gnd 3 a in 4 8 conv 7 sck 6 sdo 5 ov dd top view ts8 package 8-lead plastic tsot-23 t jmax = 150c, ja = 250c/w v dd 1 gnd 2 a in 3 6 conv 5 sdo 4 sck top view s6 package 6-lead plastic tsot-23 t jmax = 150c, ja = 250c/w pin configuration operating temperature range ltc2360c/ltc2361c/ltc2362c .............. 0c to 70c ltc2360i/ltc2361i/ltc2362i .............. C40c to 85c ltc2360h/ltc2361h/ltc2362h (note 12) .. C40c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc2362cts8#trmpbf ltc2362cts8#trpbf ltdbv 8-lead plastic tsot23 0c to 70c ltc2362its8#trmpbf ltc2362its8#trpbf ltdbv 8-lead plastic tsot23 -40c to 85c ltc2362hts8#trmpbf ltc2362hts8#trpbf ltdbv 8-lead plastic tsot23 -40c to 125c ltc2362cs6#trmpbf ltc2362cs6#trpbf ltdgp 6-lead plastic tsot23 0c to 70c ltc2362is6#trmpbf ltc2362is6#trpbf ltdgp 6-lead plastic tsot23 -40c to 85c ltc2362hs6#trmpbf ltc2362hs6#trpbf ltdgp 6-lead plastic tsot23 -40c to 125c ltc2361cts8#trmpbf ltc2361cts8#trpbf ltdgm 8-lead plastic tsot23 0c to 70c ltc2361its8#trmpbf ltc2361its8#trpbf ltdgm 8-lead plastic tsot23 -40c to 85c ltc2361hts8#trmpbf ltc2361hts8#trpbf ltdgm 8-lead plastic tsot23 -40c to 125c ltc2361cs6#trmpbf ltc2361cs6#trpbf ltdgn 6-lead plastic tsot23 0c to 70c ltc2361is6#trmpbf ltc2361is6#trpbf ltdgn 6-lead plastic tsot23 -40c to 85c ltc2361hs6#trmpbf ltc2361hs6#trpbf ltdgn 6-lead plastic tsot23 -40c to 125c ltc2360cts8#trmpbf ltc2360cts8#trpbf ltdgj 8-lead plastic tsot23 0c to 70c ltc2360its8#trmpbf ltc2360its8#trpbf ltdgj 8-lead plastic tsot23 -40c to 85c ltc2360hts8#trmpbf ltc2360hts8#trpbf ltdgj 8-lead plastic tsot23 -40c to 125c ltc2360cs6#trmpbf ltc2360cs6#trpbf ltdgk 6-lead plastic tsot23 0c to 70c ltc2360is6#trmpbf ltc2360is6#trpbf ltdgk 6-lead plastic tsot23 -40c to 85c ltc2360hs6#trmpbf ltc2360hs6#trpbf ltdgk 6-lead plastic tsot23 -40c to 125c trm = 500 pieces. *temperature grades are identi? ed by a label on the shipping container. consult ltc marketing for information on lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc2360/ltc2361/ltc2362 3 236012fa converter characteristics parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (notes 5, 6) l 0.25 1 lsb differential linearity error (note 6) l 0.25 1 lsb transition noise (note 7) 0.25 lsb rms offset error (note 6) l 13.5 lsb gain error (note 6) l 0.1 2 lsb total unadjusted error (note 6) l 1.1 3.5 lsb the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in analog input voltage s6 package ts8 package l l C0.05 C0.05 v dd + 0.05 v ref + 0.05 v i in analog input leakage current conv = high l 1 a c in analog input capacitance between conversions during conversions 20 4 pf pf v ref reference input voltage ts8 package l 1.4 v dd + 0.05 v i ref reference input leakage current ts8 package l 1 a c ref reference input capacitance ts8 package 20 pf t ap sample-and-hold aperture delay time 1 ns t jitter sample-and-hold aperture delay time jitter 0.3 ns analog input the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) dynamic accuracy the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 49khz for ltc2360/ltc2361, f in = 100khz for ltc2362 72 db snr signal-to-noise ratio f in = 49khz for ltc2360/ltc2361, f in = 100khz for ltc2362 73 db thd total harmonic distortion f in = 49khz for ltc2360/ltc2361, f in = 100khz for ltc2362 C85 db sfdr spurious free dynamic range f in = 49khz for ltc2360/ltc2361, f in = 100khz for ltc2362 86 db imd intermodulation distortion f in1 = 97khz, f in2 = 100khz for ltc2362 f in1 = 47khz, f in2 = 49khz for ltc2360/ltc2361 C75 db full-power bandwidth at 3db at 0.1db 10 2 mhz mhz full-linear bandwidth sinad 68db 1 mhz
ltc2360/ltc2361/ltc2362 4 236012fa digital inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v ih high level input voltage 2.7v < v dd 3.6v 2.35v v dd 2.7v l l 2 1.7 v v v il low level input voltage 2.7v < v dd 3.6v 2.35v v dd 2.7v l l 0.8 0.7 v v i ih high level input current v in = v dd l 2.5 a i il low level input current v in = 0v l C2.5 a c in digital input capacitance 2pf v oh high level output voltage v dd = 2.35v to 3.6v, i source = 200a l v dd C 0.2 v v ol low level output voltage v dd = 2.35v to 3.6v, i sink = 200a l 0.2 v i oz hi-z output leakage conv = v dd l 3 a c oz hi-z output capacitance conv = v dd 4pf i source output source current v out = 0v C10 ma i sink output sink current v out = v dd 10 ma power requirement the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v dd supply voltage l 2.35 3.0 3.6 v ov dd digital output supply voltage l 1.0v v dd v i dd supply current operational mode, ltc2362 operational mode, ltc2361 operational mode, ltc2360 sleep mode sleep mode sleep mode f smpl = 500ksps f smpl = 250ksps f smpl = 100ksps 0c to 70c C40c to 85c C40c to 125c l l l l l l 1.1 0.75 0.5 0.1 0.1 0.1 2 1.5 1 2 2 5 ma ma ma a a a p d power dissipation operational mode, ltc2362 operational mode, ltc2361 operational mode, ltc2360 sleep mode sleep mode sleep mode f smpl = 500ksps f smpl = 250ksps f smpl = 100ksps 0c to 70c C40c to 85c C40c to 125c l l l l l l 3.3 2.25 1.5 0.3 0.3 0.3 7.2 5.4 3.6 7.2 7.2 18 mw mw mw w w w
ltc2360/ltc2361/ltc2362 5 236012fa timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: when pins a in and v ref are taken below gnd or above v dd , they will be clamped by internal diodes. these products can handle input currents greater than 100ma below gnd or above v dd without latch-up. note 4: v dd = ov dd = v ref = 2.35v to 3.6v, f smpl = f smpl(max) and f sck = f sck(max) unless otherwise speci? ed. note 5: integral linearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. symbol parameter conditions ltc2360 ltc2361 ltc2362 units min typ max min typ max min typ max f smpl(max) maximum sampling frequency (notes 8, 9) l 100 250 500 khz f sck shift clock frequency (notes 8, 9) l 10 25 50 mhz t sck shift clock period l 100 40 20 ns t throughput minimum throughput time, t acq + t conv l 10 4 2 s t acq acquisition time l 2 1 0.5 s t conv conversion time l 8 3 1.5 s t 1 minimum positive conv pulse width (note 8) l 8 3 1.5 s t 2 sck setup time after conv (note 8) l 16 16 16 ns t 3 sdo enabled time after conv (notes 8, 9) l 16 16 16 ns t 4 sdo data valid access time after sck (notes 8, 9, 10) l 888ns t 5 sck low time (note 11) l 40% 40% 40% t sck t 6 sck high time (note 11) l 40% 40% 40% t sck t 7 sdo data valid hold time after sck (notes 8, 9, 10) l 444 ns t 8 sdo into hi-z state time after conv (notes 8, 9) 6 6 6 ns note 6: linearity, offset and gain speci? cations apply for a single-ended a in input with respect to gnd. note 7: typical rms noise at code transitions. note 8: guaranteed by characterization. all input signals are speci? ed with t r = t f = 2ns (10% to 90% of v dd ) and timed from a voltage level of 1.6v. note 9: all timing speci? cations given are with a 10pf capacitance load. with a capacitance load greater than this value, a digital buffer or latch must be used. note 10: the time required for the output to cross the v ih or v il voltage. note 11: guaranteed by design, not subject to test. note 12: high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c.
ltc2360/ltc2361/ltc2362 6 236012fa typical performance characteristics integral nonlinearity vs output code differential nonlinearity vs output code histogram for 16384 conversions supply current vs sample rate sinad vs input frequency thd vs input frequency 48khz sine wave 8192 fft plot t a = 25c, v dd = ov dd = v ref (ltc2360, note 4) output code 0 0.6 0.8 3072 3584 236012 g01 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 512 1024 1536 2048 2560 4096 C1 inl (lsb) 1 v dd = 3v output code 0 0.6 0.8 3072 3584 236012 g02 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 512 1024 1536 2048 2560 4096 C1 dnl (lsb) 1 v dd = 3v code count 10000 8000 4000 6000 2000 0 2047 2045 2049 236012 g04 2050 2046 2048 v dd = 3v sampling frequency (ksps) 0 supply current (a) 500 400 200 300 100 0 40 20 60 70 236012 g05 100 30 10 50 v dd = 3.6v 90 80 input frequency (khz) sinad (db) 236012 g07 74 73 72 70 71 69 1 100 10 v dd = 3.6v v dd = 2.35v v dd = 3.0v input frequency (khz) thd (db) 236012 g08 C78 C80 C82 C84 C90 C88 C86 C92 1 100 10 v dd = 3.6v v dd = 3.0v v dd = 2.35v input frequency (khz) 0 magnitude (db) 0 C20 C60 C100 C40 C80 C120 C140 20 40 2306012 g09 50 30 10 v dd = 3v f smpl = 100ksps integral and differential nonlinearity vs reference voltage (ts8 package) reference voltage (v) 0.8 0.6 0.8 3.2 236012 g03 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 1.2 1.6 2 2.4 2.8 3.6 C1 nonlinearity error (lsb) 1 v dd = 3.6v min dnl max dnl max inl min inl reference current vs sample rate (ts8 package) sample rate (ksps) 0 reference current (a) 20.0 16.0 8.0 12.0 4.0 0.0 40 20 60 70 236012 g06 100 30 10 50 v dd = 3.6v 90 80
ltc2360/ltc2361/ltc2362 7 236012fa differential nonlinearity vs output code typical performance characteristics t a = 25c, v dd = ov dd = v ref (ltc2361, note 4) integral nonlinearity vs output code histogram for 16384 conversions supply current vs sample rate sinad vs input frequency 124khz sine wave 8192 fft plot thd vs input frequency code count 10000 8000 4000 6000 2000 0 2047 2045 2049 236012 g13 2050 2046 2048 v dd = 3v sample rate (ksps) 0 supply current (a) 800 600 200 400 0 200 100 236012 g14 250 150 50 v dd = 3.6v input frequency (khz) sinad (db) 2306012 g16 74 72 73 70 71 69 1 100 1000 10 v dd = 3.6v v dd = 2.35v v dd = 3.0v input frequency (khz) thd (db) 236012 g17 C71 C79 C77 C75 C73 C81 C83 C89 C87 C85 C91 v dd = 3.0v 1 v dd = 3.6v 100 1000 v dd = 2.35v 10 input frequency (khz) 0 magnitude (db) 0 C20 C60 C100 C40 C80 C120 C140 50 100 2306012 g18 125 75 25 v dd = 3v f smpl = 250ksps output code 0 0.6 0.8 3072 3584 236012 g10 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 512 1024 1536 2048 2560 4096 C1 inl (lsb) 1 v dd = 3v output code 0 0.6 0.8 3072 3584 236012 g11 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 512 1024 1536 2048 2560 4096 C1 dnl (lsb) 1 v dd = 3v integral and differential nonlinearity vs reference voltage (ts8 package) reference voltage (v) 0.8 0.6 0.8 3.2 236012 g12 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 1.2 1.6 2 2.4 2.8 3.6 C1 nonlinearity error (lsb) 1 min dnl max inl min inl max dnl v dd = 3.6v reference current vs sample rate (ts8 package) sample rate (ksps) 0 reference current (a) 50.0 40.0 20.0 30.0 10.0 0.0 100 236012 g15 250 50 v dd = 3.6v 200 150
ltc2360/ltc2361/ltc2362 8 236012fa typical performance characteristics t a = 25c, v dd = ov dd = v ref (ltc2362, note 4) sinad vs input frequency 248khz sine wave 8192 fft plot thd vs input frequency input frequency (khz) sinad (db) 2306012 g25 74 72 73 70 71 69 1 100 1000 10 v dd = 3.6v v dd = 3.0v v dd = 2.35v input frequency (khz) thd (db) 2306012 g26 C67 C75 C71 C87 C79 C83 C91 1 100 1000 10 v dd = 3.6v v dd = 3.0v v dd = 2.35v input frequency (khz) 0 magnitude (db) 0 C20 C60 C100 C40 C80 C120 C140 100 200 2306012 g27 250 150 50 v dd = 3v f smpl = 500ksps differential nonlinearity vs output code output code 0 0.6 0.8 3072 3584 236012 g20 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 512 1024 1536 2048 2560 4096 C1 dnl (lsb) 1 v dd = 3v histogram for 16384 conversions supply current vs sample rate code count 10000 8000 4000 6000 2000 0 2047 2045 2049 236012 g22 2050 2046 2048 v dd = 3v sample rate (ksps) 0 supply current (a) 1200 600 800 1000 200 400 0 400 200 236012 g23 500 300 100 v dd = 3.6v integral nonlinearity vs output code output code 0 0.6 0.8 3072 3584 236012 g19 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 512 1024 1536 2048 2560 4096 C1 inl (lsb) 1 v dd = 3v integral and differential nonlinearity vs reference voltage (ts8 package) reference current vs sample rate (ts8 package) reference voltage (v) 0.8 0.6 0.8 3.2 236012 g21 C0.4 C0.2 0 0.2 0.4 C0.8 C0.6 1.2 1.6 2 2.4 2.8 3.6 C1 nonlinearity error (lsb) 1 v dd = 3.6v min dnl max inl min inl max dnl sample rate (ksps) 0 reference current (a) 80.0 60.0 20.0 40.0 0.0 100 236012 g24 500 50 v dd = 3.6v 200 250 300 350 400 450 150
ltc2360/ltc2361/ltc2362 9 236012fa pin functions s6 package v dd (pin 1): positive supply. the v dd range is 2.35v to 3.6v. v dd also de? nes the input span of the adc, 0v to v dd . bypass to gnd and to a solid ground plane with a 2.2f ceramic capacitor (or 2.2f tantalum in parallel with 0.1f ceramic). gnd (pin 2): ground. the gnd pin must be tied directly to a solid ground plane. a in (pin 3): analog input. a in is a single-ended input with respect to gnd with a range from 0v to v dd . sck (pin 4): shift clock input. the sck serial clock syn- chronizes the serial data transfer. sdo data transitions on the falling edge of sck. sdo (pin 5): three-state serial data output. the a/d conversion result is shifted out on sdo as a serial data stream with msb ? rst. the data stream consists of 12 bits of conversion data followed by trailing zeros. conv (pin 6): convert input. this active high signal starts a conversion on the rising edge. the device automatically powers down after conversion. a logic low on this input enables the sdo pin, allowing the data to be shifted out. ts8 package v dd (pin 1): positive supply. the v dd range is 2.35v to 3.6v. bypass to gnd and to a solid ground plane with a 2.2f ceramic capacitor (or 2.2f tantalum in parallel with 0.1f ceramic). v ref (pin 2): reference input. v ref de? nes the input span of the adc, 0v to v ref . the v ref range is 1.4v to v dd . bypass to gnd and to a solid ground plane with a 2.2f ceramic capacitor (or 2.2f tantalum in parallel with 0.1f ceramic). gnd (pin 3): ground. the gnd pin must be tied directly to a solid ground plane. a in (pin 4): analog input. a in is a single-ended input with respect to gnd with a range from 0v to v ref . ov dd (pin 5): output driver supply for sdo. the ov dd range is 1v to v dd . bypass to gnd and to a solid ground plane with a 2.2f ceramic capacitor (or 2.2f tantalum in parallel with 0.1f ceramic). ov dd can be driven separately from v dd and ov dd can be higher than v dd . sdo (pin 6): three-state serial data output. the a/d conversion result is shifted out on sdo as a serial data stream with msb ? rst. the data stream consists of 12 bits of conversion data followed by trailing zeros. sck (pin 7): shift clock input. the sck serial clock syn- chronizes the serial data transfer. sdo data transitions on the falling edge of sck. conv (pin 8): convert input. this active high signal starts a conversion on the rising edge. the device automatically powers down after conversion. a logic low on this input enables the sdo pin, allowing the data to be shifted out.
ltc2360/ltc2361/ltc2362 10 236012fa block diagram 236012 f01 t 8 hi-z 1.6v conv sdo figure 1. sdo into hi-z state after conv rising edge figure 2. sdo data valid hold time after sck falling edge figure 3. sdo data valid acess time after sck falling edge v ih 236012 f02 v il t 7 1.6v sck sdo v ih 236012 f03 v il t 4 1.6v sck sdo timing diagrams 12-bit adc v dd a in s and h analog input range 0v to v ref three-state serial output port timing logic 6 7 sdo sck conv 236012 bd 8 2.2f 1 4 2 v ref 3 gnd ov dd 2.2f 5 2.2f ts8 package + +
ltc2360/ltc2361/ltc2362 11 236012fa applications information dc performance the noise of an adc can be evaluated in two ways: sig- nal-to-noise ratio (snr) in the frequency domain and histogram in the time domain. the ltc2360/ltc2361/ ltc2362 excel in both. figure 5 demonstrates that the ltc2360/ltc2361/ltc2362 have an snr of over 73db. the noise in the time domain histogram is the transition noise associated with a 12-bit resolution adc which can be measured with a ? xed dc signal applied to the input of the adc. the resulting output codes are collected over a large number of conversions. the shape of the distribu- tion of codes will give an indication of the magnitude of the transition noise. in figure 4, the distribution of output codes is shown for a dc input that has been digitized 16384 times. the distribution is gaussian and the rms code transition is about 0.32lsb. this corresponds to a noise level of 73db relative to a full scale of 3v. dynamic performance the ltc2360/ltc2361/ltc2362 have excellent high speed sampling capability. fast fourier transform (fft) test techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequencies outside the fundamental. figures 5 and 6 show typical ltc2361 and ltc2362 fft plots respectively. figure 4. histogram for 16384 conversions figure 5. ltc2361 fft plot figure 6. ltc2362 fft plot input frequency (khz) 0 magnitude (db) 0 C20 C60 C100 C40 C80 C120 C140 50 100 236012 f05 125 25 75 v dd = 3v f smpl = 250ksps f in = 124khz sinad = 73db thd = C84db input frequency (khz) 0 magnitude (db) 0 C20 C60 C100 C40 C80 C120 C140 100 200 236012 f06 250 50 150 v dd = 3v f smpl = 500ksps f in = 248khz sinad = 73db thd = C81db code count 10000 8000 4000 6000 2000 0 2047 2045 2049 236012 f04 2050 2046 2048 v dd = 3v
ltc2360/ltc2361/ltc2362 12 236012fa applications information signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency to the rms amplitude of all other fre- quency components at the a/d output. the output is band limited to frequencies from above dc and below half the sampling frequency. figure 6 shows a typical fft with a 500khz sampling rate and a 248khz input. the dynamic performance is excellent for input frequencies up to and beyond the nyquist frequency of 250khz. effective number of bits the effective number of bits (enob) is a measurement of the resolution of an adc and is directly related to sinad by the equation: enob = sinad ? 1.76 6.02 where enob is the effective number of bits of resolution and sinad is expressed in db. at the maximum sampling rate of 500khz, the ltc2362 maintains enob above 11 bits up to the nyquist input frequency of 250khz (refer to figure 7). total harmonic distortion the total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log v 2 2 + v 3 2 + v 4 2 + ...v n 2 v 1 where v 1 is the rms amplitude of the fundamental frequency and v 2 through v n are the amplitudes of the second through nth harmonics. thd vs input frequency is shown in figure 8. the ltc2362 has excellent distortion performance up to the nyquist frequency and beyond. figure 7. ltc2362 enob and sinad vs input frequency figure 8. ltc2362 thd vs input frequency input frequency (khz) sinad (db) enob 2306012 f07 74 72 73 70 71 12 67 69 68 11.67 11.34 11 1 100 1000 10 v dd = 3.6v v dd = 3.0v v dd = 2.35v input frequency (khz) thd (db) 2306012 f08 C67 C75 C71 C87 C79 C83 C91 1 100 1000 10 v dd = 3.6v v dd = 3.0v v dd = 2.35v
ltc2360/ltc2361/ltc2362 13 236012fa applications information intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermoduation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies f a and f b are applied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mf a nf b , where m and n = 0, 1, 2, 3, etc. for example, the 2nd order imd terms include (f a f b ). if the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order imd products can be expressed by the following formula: imd f a f b () = 20log amplitude at f a f b () amplitude at f a peak harmonic or spurious noise the peak harmonic or spurious noise is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full-scale input signal. full-power and full-linear bandwidth the full-power bandwidth is that input frequency at which the amplitude of reconstructed fundamental is reduced by 3db for full-scale input signal. the full-linear bandwidth is the input frequency at which the sinad has dropped to 68db (11 effective bits). the ltc2362 has been designed to optimize input bandwidth, allowing the adc to undersample input signals with frequencies above the converters nyquist frequency. the noise ? oor stays very low at high frequencies; sinad becomes dominated by distortion at frequencies far beyond nyquist. figure 9. ltc2362 intermodulation distortion plot input frequency (khz) 0 magnitude (db) 0 C20 C60 C100 C40 C80 C120 100 200 236012 f09 250 50 150 v dd = 3.6v f smpl = 500ksps f a = 99khz f b = 101khz imd = C76.5db
ltc2360/ltc2361/ltc2362 14 236012fa applications information overview the ltc2360/ltc2361/ltc2362 use a successive ap- proximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output. all devices operate from a single 2.35v to 3.6v supply. the conversion time of the devices is controlled by an internal oscillator, which allows the ltc2360/ltc2361/ltc2362 to sample at a rate of 100ksps, 250ksps and 500ksps respectively. the ltc2360/ltc2361/ltc2362 contain a 12-bit, switched- capacitor adc, a sample-and-hold, a serial interface (see block diagram) and are available in tiny 6- or 8-lead tsot-23 packages. the s6 package of the ltc2360/ltc2361/ltc2362 uses v dd as the reference and has an analog input range of 0v to v dd . the adc samples the analog input with respect to gnd and outputs the result through the serial interface. the ts8 package provides two additional pins: a reference pin, v ref , and an output supply pin, ov dd . the adc can operate with reduced spans down to 1.4v and achieve 342v resolution. ov dd controls the output swing of the digital output pin, sdo, and allows the device to com- municate with 1.8v, 2.5v or 3v digital systems. serial interface the ltc2360/ltc2361/ltc2362 communicate with micro- controllers, dsps and other external circuitry via a 3-wire interface. figure 10 shows the operating sequence of the serial interface. data transfer a rising conv edge starts a conversion and disables sdo. after the conversion, the adc automatically goes into sleep mode, drawing only leakage current. conv going low enables sdo and clocks out the msb bit, b11. sck then synchronizes the data transfer with each bit being transmitted on the falling sck edge and can be captured on the rising sck edge. after completing the data transfer, if further sck clocks are applied with conv low, sdo will output zeros inde? nitely (see figure 10). for example, 16-clocks at sck will produce the 12-bit data and four trailing zeros on sdo. sleep mode the ltc2360/ltc2361/ltc2362 enter sleep mode to save power after each conversion if conv remains high. in sleep mode, all bias currents are shut down and only leakage currents remain (about 0.1a). the sample-and-hold is in hold mode while the adc is in sleep mode. the adc returns to sample mode after the falling edge of conv during power-up (see figure 10). exiting sleep mode and power-up time by taking conv low, the adc powers up and acquires an input signal completely after the aquisition time (t acq ). after t acq , the adc can perform a conversion as described in the serial interface section (see figure 10). 1 recommended high or low hi-z state 234 t 6 t 5 t 4 t 7 t 8 236012 f10 t 3 9101112 b11 (msb) *after completing the data transfer, if further sck clocks are applied with conv low, the adc will output zeros indefinitely by taking conv low, the device powers up and acquires an input accurately after t acq sleep mode t conv conv sck sdo t 1 t acq t throughput t 2 b10 b9 b3 b2 b1 b0* figure 10. ltc2360/ltc2361/ltc2362 serial interface timing diagram
ltc2360/ltc2361/ltc2362 15 236012fa applications information achieving micropower performance with typical operating currents of 0.5ma, 0.75ma and 1.1ma for the ltc2360/ltc2361/ltc2362 and automati- cally entering sleep mode right after a conversion, these devices achieve extremely low power consumption over a wide range of sample rates (see figure 11). the sleep mode allows the supply current to drop with reduced sample rate. several things must be taken into account to achieve such low power consumption. minimize power consumption in sleep mode the ltc2360/ltc2361/ltc2362 enter sleep mode after each conversion if conv remains high and draw only leakage current (see figure 10). if the conv input is not running rail-to-rail, the input logic buffer will draw current. this current may be large compared to the typical supply current. to obtain the lowest supply current, bring the conv pin to gnd when it is low and to v dd when it is high. after the conversion with conv staying high, the converter is in sleep mode and draws only leakage current. the status of the sck input has no effect on supply current during this time. for the best performance, hold sck either high or low while the adc is converting. minimize the device active time in systems that have signi? cant time between conversions, the adc draws a minimal amount of power. figures 12 and 13 show two ways to minimize the amount of time the adc draws power. in figure 12, the adc draws power during t acq and t conv and is in sleep mode for the rest of the time. the conversion results are available at the next conv falling edge. in figure 13, the adc draws twice the power than that in figure 12, but the conversion results are available during t data . the user can use the fastest sck available in the system to shorten data transfer time, t data as long as t 4 and t 7 are not violated. sdo loading capacitive loading on the digital output can increase power consumption. a 100pf capacitor on the sdo pin can add more than 50a to the supply current at a 200khz clock frequency. an extra 50a or so of current goes into charg- ing and discharging the load capacitor. the same goes for digital lines driven at a high frequency by any logic. the c ? v ? f currents must be evaluated with the troublesome ones minimized. figure 11. supply current vs sample rate recommended high or low hi-z state 236012 f12 b11 conv sck sdo 12349101112 b10 b9 b3 b2 b1 b0 sampling input and transferring data executing a conversion and putting the device into sleep mode t acq t conv sleep mode t throughput = t acq + t conv + t sleepmode figure 12. minimize the time when the device draws power, while the conversion results are available after the device wakes up sample rate (ksps) supply current (a) 236012 ta01b 1200 1000 800 400 600 200 0 1 100 1000 10 v dd = ov dd = v ref = 3.6v t a = 25 c ltc2361 ltc2362 ltc2360
ltc2360/ltc2361/ltc2362 16 236012fa single-ended analog input driving the analog input the analog input of the ltc2360/ltc2361/ltc2362 is easy to drive. the input draws only one small current spike while charging the sample-and-hold capacitor with the adc going into track mode. during the conversion, the analog input draws only a small leakage current. if the source impedance of the driving circuit is low, then the input of the ltc2360/ltc2361/ltc2362 can be driven directly. as source impedance increases, so will acquisi- tion time. for minimum acquisition time with high source impedance, a buffer ampli? er should be used. the main requirement is that the ampli? er driving the analog input must settle after the small current spike before the next conversion starts (settling time must be less than t acq for full throughput rate). while choosing an input ampli- ? er, also keep in mind the amount of noise and harmonic distortion the ampli? er contributes. choosing an input ampli? er choosing an input ampli? er is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the ampli? er from charging the sampling capacitor, choose an ampli? er that has a low output impedance (<100 ) at the closed-loop bandwidth frequency. for example, if an ampli? er is used in a gain of 1 and has a unity-gain bandwidth of 10mhz, then the output impedance at 10mhz must be less than 100 . the second requirement is that the closed-loop bandwidth must be greater than 8mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc2360/ltc2361/ltc2362 will depend on the application. generally, applications fall into two categories: ac applications where dynamic speci? cations are most critical and time domain applications where dc accuracy and settling time are most critical. the follow- ing list is a summary of the op amps that are suitable for driving the ltc2360/ltc2361/ltc2362. (more detailed information is available on the linear technology website at www.linear.com.) ltc1566-1: low noise 2.3mhz continuous time low- pass filter. lt ? 1630: dual 30mhz rail-to-rail voltage fb ampli? er. 2.7v to 15v supplies. very high a vol , 500v offset and 520ns settling to 0.5lsb for a 4v swing. thd and noise are C93db to 40khz and below 1lsb to 320khz (a v = 1, 2v p-p into 1k, v s = 5v), making the part excellent for ac applications (to 1/3 nyquist) where rail-to-rail perfor- mance is desired. quad version is available as lt1631. ltc6241: dual 18mhz, low noise, rail-to-rail, cmos voltage fb ampli? er. 2.8v to 6v supplies. very high a vol and 125v offset. it is suitable for applications with a single 5v supply. quad version is available as ltc6242. lt1797: unity-gain stable 10mhz, rail-to-rail voltage feedback ampli? er. lt1801: 180mhz gbwp , C75dbc at 500khz, 2ma/ampli- ? er, 8.5nv/ hz . lt6203: 100mhz gbwp , C80dbc distortion at 1mhz, unity- gain stable, r-r in and out, 3ma/ampli? er, 1.9nv/ hz . applications information recommended high or low hi-z state 236012 f13 b11 conv sck sdo 12349101112 b10 b9 b3 b2 b1 b0 data transfer acquire input execute conversion executing a dummy conversion and put the device into sleep mode t data t conv t conv t acq sleep mode t throughput = t acq + 2 ? t conv + t data + t sleepmode recommended high or low figure 13. minimize the time when the device draws power, while the conversion results are available right after conversion
ltc2360/ltc2361/ltc2362 17 236012fa input filtering and source impedance the noise and the distortion of the input ampli? er and other circuitry must be considered since they will add to the ltc2360/ltc2361/ltc2362 noise and distortion. the small-signal bandwidth of the sample-and-hold circuit is 10mhz. any noise or distortion products that are pres- ent at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be ? ltered prior to the analog inputs to minimize noise. a simple 1-pole rc ? lter is suf? cient for many applications. for example, figure 14 shows a 220pf capacitor from a in to ground and a 51 source resistor to limit the input bandwidth to 10mhz. the 220pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sampling-glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silvermica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal ? lm surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole ? lter is required. high external source resistance, combined with the 20pf of input capacitance, will reduce the rated 10mhz bandwidth and increase acquisition time beyond 500ns. applications information reference input on the ts8 package of the ltc2360/ltc2361/ltc2362, the voltage on the v ref pin de? nes the full-scale range of the adc. the reference voltage can range from v dd down to 1.4v. input range the analog input of the ltc2360/ltc2361/ltc2362 is driven single-ended with respect to gnd from a single supply. the input may swing up to v dd for the s6 package and to v ref for the ts8 package. the 0v to 2.5v range is also ideally suited for single-ended input use with v dd or v ref = 2.5v for single supply applications. if the difference between the a in input and gnd exceeds v dd for the s6 package or v ref for the ts8 package, the output code will stay ? xed at all ones, and if this difference goes below 0v, the output code will stay ? xed at all zeros. figure 15 shows the ideal input/output characteristics for the ltc2360/ltc2361/ltc2362. the code transitions oc- cur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, , fs C 1.5lsb). the output code is straight binary with 1lsb = v dd /4096 for the s6 package and 1lsb = v ref /4096 for the ts8 package. v dd gnd a in conv sdo sck 1 2 3 6 5 4 ltc2362 220pf 51 2.2f 236012 f14 figure 14. rc input filter input voltage (v) 0 1lsb unipolar output code 111...111 111...110 236012 f15 000...001 000...000 fs C 1lsb figure 15. transfer characteristics
ltc2360/ltc2361/ltc2362 18 236012fa applications information board layout and bypassing wire wrap boards are not recommended for high resolution and/or high speed a/d converters. to obtain the best per- formance from the ltc2360/ltc2361/ltc2362, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. the analog input should be screened by the ground plane. high quality tantalum and ceramic bypass capacitors should be used at the v dd pin as shown in the block diagram on the ? rst page of this data sheet. for optimum performance, a 2.2f surface mount avx capacitor with a 0.1f ceramic is recommended for the v dd and v ref pins. alternatively, 2.2f ceramic chip capacitors such as murata grm235y5v106z016 may be used. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. figure 16 shows the recommended system ground con- nections. all analog circuitry grounds should be terminated at the ltc2360/ltc2361/ltc2362. the ground return from the ltc2360/ltc2361/ltc2362 to the power supply should be low impedance for noise free operation. digital circuitry grounds must be connected to the digital supply common. in applications where the adc data outputs and control sig- nals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the micropro- cessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. figure 16. power supply ground practice 236012 f16 gnd a in v dd ca in conv sdo sck cv dd pin 1 vias to ground plane + 2.2f
ltc2360/ltc2361/ltc2362 19 236012fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description s6 package 6-lead plastic tsot-23 (reference ltc dwg # 05-08-1636) 1.50 C 1.75 (note 4) 2.80 bsc 0.30 C 0.45 6 plcs (note 3) datum a 0.09 C 0.20 (note 3) s6 tsot-23 0302 rev b 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637) 1.50 C 1.75 (note 4) 2.80 bsc 0.22 C 0.36 8 plcs (note 3) datum a 0.09 C 0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.52 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc2360/ltc2361/ltc2362 20 236012fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0809 rev a ? printed in usa related parts typical application part number description comments adcs ltc1403/ltc1403a 12-/14-bit, 2.8msps serial sampling adc 3v, differential input, 12mw, msop package ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, 14mw, msop package ltc1860 12-bit, 250ksps serial adc 5v supply, 1-channel, 4.3mw, msop-8 package ltc1860l 12-bit, 150ksps serial adc 3v supply, 1-channel, 1.3mw, msop-8 package ltc1861 12-bit, 250ksps serial adc 5v supply, 2-channel, 4.3mw, msop-8 package ltc1861l 12-bit, 150ksps serial adc 3v supply, 2-channel, 1.3mw, msop-8 package ltc1863 12-bit, 200ksps serial adc 8-channel adc 5v supply, 6.5mw, ssop-16 package, pin compatible to ltc1863l, ltc1867 ltc1863l 12-bit, 250ksps serial adc 8-channel adc 5v supply, 2.2mw, ssop-16 package, pin compatible to ltc1863, ltc1867l ltc1864/ltc1865 16-bit, 250ksps serial adc 5v supply, 1 and 2 channel, 4.3mw, msop package ltc1867 16-bit, 200ksps serial adc 8-channel adc 5v supply, 6.5mw, ssop-16 package, pin compatible to ltc1863, ltc1867l ltc1867l 16-bit, 175ksps serial adc 8-channel adc 3v supply, 2.2mw, ssop-16 package, pin compatible to ltc1863l, ltc1867 ltc2355/ltc2356 12-/14-bit, 3.5msps serial adcs 3.3v supply, differential input, 18mw, msop package ltc2365/ltc2366 12-bit, 1/3 msps serial adcs in tsot23 2.35v to 3.6v supply, pin and software compatible to ltc2360/ltc2361/ltc2362 dacs ltc1592 16-bit, serial softspan? i out dac 1lsb inl/dnl, software selectable spans ltc1666/ltc1667/ltc1668 12-/14-/16-bit, 50msps dacs 87db sfdr, 20ns settling time ltc2630 12-/10-/8-bit single v out dacs sc70 6-pin package, internal reference, 1lsb inl (12 bits) references lt1460-2.5 micropower series voltage reference 0.1% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.05% initial accuracy, 3ppm drift lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift lt6660 ultra-tiny micropower series reference 2mm 2mm dfn package, 0.2% initial accuracy, 10ppm drift softspan is a trademark of linear technology corporation. recommended ac test circuitry for the ltc2362 4.7f 1.5v ac input 50 5% 1k 1% 1k 1% 220pf 2200pf 236012 ta02 to mcu ltc2362 conv sck sdo a in v dd 3v gnd 4.7f 2.2f + +

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